Comment by andrewcooke

i'm not sure they're as different as you are making out. why couldn't you have a chip that's somewhere between a cpu, a gpu and an asic - it rewires itself to make a trade-off between cache+prediction v many alus+parallelism? maybe the asic part is a bit extreme, but fermi (the next gen nvidia) will have on-chip memory that is switchable between explicit local shared memory (gpu) and implicit local cache (cpu). why couldn't the same kind of flexible approach be made to instructions - longer+fewer v more+shorter pipelines?