Comment by vetinari
7 years ago
NaN-boxed or tagged pointers have to be processed before use anyway - amd64 enforces canonical pointers, even if the high bits are unused (they have to be set to 1).
Aarch64 on the other way...
7 years ago
NaN-boxed or tagged pointers have to be processed before use anyway - amd64 enforces canonical pointers, even if the high bits are unused (they have to be set to 1).
Aarch64 on the other way...
What's your point? A few bitwise operations are far quicker than reading from memory. Also are you sure that the high bits must be 1? I thought they had to be the same as the 48th bit.
You are right - they can be 0 & copy of bit 47.
The point was, that there will be not a problem with tagged pointers. The pointers have to be clean today when used, so those who use tagged pointers have a place in their code where they handle the cleaning.
I believe the new garbage collector for the JVM colors pointers in a way they are not scrubbed before use; they memory (re-)map into multiple regions to implement read and write barriers.
Some very old distributed systems used 64 bit pointers where the upper bits told you what machine the data was on.
And we have Intel putting SSD card in DIMM slots. I expect there are semantics attached to those address ranges as well.
I dunno where we are after Spectre, but one of the microkernel architectures got its IPC speed by packing most processes into a couple of address spaces, only with different read write access. On preemption the TLB wasn’t invalidated (about half the cost), just modified.
These are the sorts of tricks you do when your address space is bigger than you will ever need. I expect to see more of this as time goes on. And if we ever see 128 bit pointers, expect crazy stuff like this to be de rigeur.