> So far, the bit and byte shifters only shift bits in one direction. However, bits need to be shifted in both directions. One of the key innovations of the 8087's shifter is its bidirectional design: data can be passed through the shifter in reverse to shift bits the opposite direction. This is possible because the shifter is constructed with pass transistors, not logic gates.
That's really cool. I've never really looked at ASIC design so that wasn't something I had considered before. I have a left-shift unit design that uses 74F logic, and to get it to do right shifts I would have to reverse the input and output, which is the typical trick to use when you have to use logic gates.
I have always been fascinated by a paper on barrel shifters myself. I think you would enjoy this as well: https://www.princeton.edu/~rblee/ELE572Papers/Fall04Readings...
In particular, logarithmic barrel shifters are amazingly simple to implement better than a massive multiplexer for each shift step.
Edit: oops, after further investigation it looks like you may be doing this in your design?
I have a verilog module that implements the "Mux-Based Data Reversal" design with overflow output. Yosys/nextpnr synthesize it with a 102MHz timing estimate on the lattice ice40hx8k.
As for the 74F design, yeah, it uses the logarithmic approach. It still has massive multiplexers, but there's only 5 stages for a full 32 bit shift, plus the extra gates to handle the carry bit.
Another approach you might try is to start with a rotator, then mask off the leading or trailing bits for right or left shifts. (Rotate right by X is the same as rotate left by N-X.)
I chose the mux-based approach because it has the better area*delay product, but it might be interesting to implement the mask-based design to see how it works out on my FPGA.
Interesting article! One thing I'm curious about: I can see what the bit shifter was for, but the article also mentions a separate byte shifter. What was that for?
It's for shifting by more than 7 bits. The shift is split mod 8 bits into a bit and byte portion to reduce the geometric complexity of the circuit (and perhaps help it meet timing).
> So far, the bit and byte shifters only shift bits in one direction. However, bits need to be shifted in both directions. One of the key innovations of the 8087's shifter is its bidirectional design: data can be passed through the shifter in reverse to shift bits the opposite direction. This is possible because the shifter is constructed with pass transistors, not logic gates.
That's really cool. I've never really looked at ASIC design so that wasn't something I had considered before. I have a left-shift unit design that uses 74F logic, and to get it to do right shifts I would have to reverse the input and output, which is the typical trick to use when you have to use logic gates.
http://www.pnnk.org/img/lshift_schematic.pdf
http://www.pnnk.org/img/lshift_board.png
I have always been fascinated by a paper on barrel shifters myself. I think you would enjoy this as well: https://www.princeton.edu/~rblee/ELE572Papers/Fall04Readings... In particular, logarithmic barrel shifters are amazingly simple to implement better than a massive multiplexer for each shift step.
Edit: oops, after further investigation it looks like you may be doing this in your design?
Oh, nice paper! I had been looking at this one, also by Matthew Pillmeier: https://preserve.lehigh.edu/cgi/viewcontent.cgi?article=1714...
I have a verilog module that implements the "Mux-Based Data Reversal" design with overflow output. Yosys/nextpnr synthesize it with a 102MHz timing estimate on the lattice ice40hx8k.
As for the 74F design, yeah, it uses the logarithmic approach. It still has massive multiplexers, but there's only 5 stages for a full 32 bit shift, plus the extra gates to handle the carry bit.
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Another approach you might try is to start with a rotator, then mask off the leading or trailing bits for right or left shifts. (Rotate right by X is the same as rotate left by N-X.)
I chose the mux-based approach because it has the better area*delay product, but it might be interesting to implement the mask-based design to see how it works out on my FPGA.
1 reply →
Interesting article! One thing I'm curious about: I can see what the bit shifter was for, but the article also mentions a separate byte shifter. What was that for?
It's for shifting by more than 7 bits. The shift is split mod 8 bits into a bit and byte portion to reduce the geometric complexity of the circuit (and perhaps help it meet timing).