Comment by monocasa

The micron whitepaper you cited talks about how their higher tier strategy involves keeping enough capacitance around to write out the FTL, because it's DRAM copy is allowed to get out of sync when the write-cache is enabled.

> The hold-up circuitry also preserves enough time and energy to ensure that the FTL addressing table is properly saved to the NAND. This thorough amount of data protection not only ensures data integrity in unexpected power-loss events, but it also enables the system designer to leave the SSD’s write cache enabled, giving a significant advantage in data throughput speeds.