I was wondering about that too, maybe they are relying on ECC memory to patch those over. The main page doesn't say, but in one of the comments here it says ECC memory is supported.
NAND also suffers from read disturbance; since they are emulating NAND devices, it seems reasonable to assume the FTL in the controller will be tracking reads as well as writes and refreshing blocks accordingly.
I was wondering about that too, maybe they are relying on ECC memory to patch those over. The main page doesn't say, but in one of the comments here it says ECC memory is supported.
https://ddramdisk.store/2023/01/19/the-ddr4-pcie-x8-lady-has...
NAND also suffers from read disturbance; since they are emulating NAND devices, it seems reasonable to assume the FTL in the controller will be tracking reads as well as writes and refreshing blocks accordingly.