Comment by peter_d_sherman
3 years ago
I like the idea of using multiple FPGAs to ["fanout"/"cascade"/"distribute"/"one-to-many proxy" -- choose the terminology you like best] the SM2262EN to multiple sticks of DDR3 RAM...
I'd be curious though, if the SM2262EN itself couldn't be replaced by yet another FPGA, and, if so, if the FPGA used for that purpose could be the exact same type as the other four...
If so -- then one could sort of think of that arrangement as sort of like a Tree Data Structure -- that is 2 levels deep...
But what would happen if we could make it 3 or more levels deep?
?
In other words, if we had 4 such boards and we wanted to chain them -- then we'd need another central memory controller (another FPGA ideally) -- to act as the central hub in that hierarchy...
It would be interesting, I think, to think of a future hardware architecture which allows theoretically infinite upscaling via adding more nested sub-levels/sub-components/"sub-trees" (subject to space and power and max signal path lengths and other physical constraints, of course...)
I also like the idea of an FPGA proxy between a memory controller and RAM... (what other possibilities could emerge from this?)
Anyway, an interesting device!
You can implement an SSD controller in an FPGA. That's how all the early server SSDs were implemented. I think my Fusion ioScale was one of them.
It's just an enormous amount of effort. This already looks like a huge amount of engineering to do for what must be a very niche product.
Define "an enormous amount of effort" ?
(What one person considers "effort" -- might very well be considered a relaxing and pleasurable and interesting exercise -- by another...
For example, some people hate Math and consider performing Mathematical operations "effort" -- whereas some people love Math and could spend all day at it(!) -- and find the whole process relaxing and stimulating!
It all depends on a given person's interest or disinterest, their affinity or aversion -- to a given line of endeavor...)
So, define "an enormous amount of effort" ?
Point taken, and I expect it's relevant to the author as I doubt even they thought this project was the most monetarily profitable use of their time.
How much effort? I do not know precisely, not having done it before. The relevant NVMe specifications add up to about 1000 pages, which is actually less than I expected. I suspect implementing all of that would take a rather long time regardless, and that's just the host-interface protocols. The harder part, I believe, is the implementation of the controller log itself. I intuit this based on the large visible effort the SSD industry has spent on various hardware and firmware improvements over the last decade. I don't have a good way to summarize it. The question is how much of that effort is necessary when using DRAM rather than NAND? Maybe you don't need sophisticated ECC, bad block detecting, block remapping, garbage collecting, etc.
I am pretty confident, however, that the author knows more about it than I do and their conclusion has been that it's worth using an existing SSD controller.
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