Comment by addaon
2 years ago
This comes up all the time in the context of DRAM routing. See e.g. the first image at https://resources.altium.com/p/pcb-routing-guidelines-ddr4-m....
2 years ago
This comes up all the time in the context of DRAM routing. See e.g. the first image at https://resources.altium.com/p/pcb-routing-guidelines-ddr4-m....
Okay in this case impedance matching is more important than the time delay. Thanks for the link :)