Comment by luyu_wu
2 years ago
They're horribly fragmented (there's many ISA extensions that accomplish the same thing from different companies), and thus a headache to deal with for any compiler (which is why the compiler support sucks).
2 years ago
They're horribly fragmented (there's many ISA extensions that accomplish the same thing from different companies), and thus a headache to deal with for any compiler (which is why the compiler support sucks).
There is one standard vector extension, and one company that released two chips with a non standard pre ratification version of the extension.
It was released almost two years before the first rvv 1.0 hardware became available at the end of last year. Without out it, we wouldn't have had any hardware at all.
rvv 1.0 has quite good upstream compiler support already, and before that the t-head had custom compilers that supported their rvv 0.7.1 version of the vector extension.
Now upstream gcc supports it as an alternative codegen target as well, so you can write rvv 1.0 vector instrinsics and compile those to the thead rvv 0.7.1 implementation.
I'm not aware of any company that plans to release a non rvv 1.0 rvv implementation.
Each time somebody is spitting on risc-v vector extension, it is the same false argument of fragmentation, and each time somebody fixes it with the real truth (pre-ratification of some vendors).
Arm/x86 fan boys?
"Real truth" and "fan boys"? Let's have some facts: there are indeed a boatload of extensions, though perhaps not (yet) to the V extension itself.
T-HEAD [1], Ventana's ternary op [2], Sifive also has a couple [3], including "Xsfvfwmaccqqq", one of at least four completely different matmul variants.
In particular for the latter, I would say fragmentation is an absolutely valid concern at the moment.
[1]: https://github.com/T-head-Semi/thead-extension-spec [2]: https://github.com/ventanamicro/ventana-custom-extensions/re... [3]: https://www.sifive.com/documentation
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