Comment by eigenform

The authors' hypothesis about the STLF case:

> Considering the affected core (i.e., Cortex-A715) dispatches 5 instructions in a cycle [ 55], it is likely that the CPU cannot detect the dependency if the store and load instructions are executed in the same cycle, since the store information is not yet written to the internal buffers.

> If Len(GAP) is 4 or more, the store and load instructions are executed in the different cycles, and the CPU can detect the dependency. Therefore, the CPU skips the tag check and always forwards the data from the store to load instructions.

> If Len(GAP) is less than 4, the store and load instructions are executed in the same cycle, and the CPU fails to detect the dependency and performs the tag check for the load instruction. In this case, the forwarding is blocked on tag check faults.

This would mean there's no forwarding from stores to loads within the same dispatch group on these cores?