The Ryzen 1600X is my current desktop and the computer I ran the RTL simulation on.
At the same clock frequency XiangShanV2 is quite competitive with the Zen1 CPU, however it doesn't implement the RISC-V vector extension, so will be a lot slower in any SIMD workloads. The RuyiBook is supposed to clock at 2.5GHz, but there were slides saying it can go up to 2.8GHz, while the 1600X can go up to 3.7GHz.
XiangShanV3 is a lot faster, and does implement the RISC-V vector extension, as well the hypervisor extension. They also target a 3GHz frequency.
There were a few talks at RISC-V Summit Chine regarding XiangShanV3 implementation details. Here is a recording, look at the second Day 2, if the clunky interface works for you: https://www.c114.com.cn/live/t850.html
They also present at this years hotchips in a few days.
Yeah, it won't be usable for people who want to optimize SIMD support for RISC-V.
However it does have a few extensions we haven't seen in hardware yet, like all scalar cryptography extensions. And it should perform quite similar to the Raspberry Pi 5.
are we really going to recompile all our operating systems, software and embedded firmware and move to RISC-V to save SoC designers royalties to ARM? We have ARM SBCs, accelerators, servers and laptops. Finally a common ISA and we're throwing it out why? because of some virtue signaling from Berkeley. it's a spectacular waste of time and will fail IMO
It's already succeeded in the embedded world, displacing not only a lot of use of Arm, but also pretty much killing off all other custom ISAs that some company engineer invented in order to not have to go through the hassle of licensing a core. All the major FPGA companies now offer a fully-supported RISC-V soft core as well as cores with their proprietary ISAs, and several FPGA companies already offer chips with RISC-V hard cores. In ASICs Synopsys now offers ARC-V and Cadence has some deals in place.
In applications processors chips about to come out in the next 12 months, such as this XiangShan and the SG2380, are getting up into the performance level of 10 year old Zen and Core i5 etc, which is still a perfectly fine performance level for many people and uses.
Linux has been available for RISC-V for many years, a number of distros have 2nd tier support for RISC-V, probably moving to 1st tier soon.
Android is working towards 1st class support for RISC-V, with the desired ISA extensions, fast enough hardware, and full software porting looking to converge into competitive products around 2026-2027.
Arm is NOT a "common ISA". It is proprietary and support can be arbitrarily removed at any time. Since 2023, Arm's highest performance CPU cores have dropped support for the 32 bit ISA(s) even for user programs. That's orphaning an almost 40 year history of 32 bit Arm software, restricting it to being used only on legacy CPUs which will rapidly have much less performance than newer high end CPUs.
At the same time, the low end Arm microcontroller family remains 32 bit only. And the 32 bit and 64 bit ISAs are totally different to each other.
RISC-V vendors on the other hand are happy to license you a 64 bit core with Cortex-M0 or Cortex-M3 size and features. These are often valuable as a control processor in a bigger chip with 64 bit applications processors and >32 bit address space.
In RISC-V the 32 bit and 64 bit ISAs are almost identical and it's very cheap and easy to support 32 bit code on a 64 bit CPU -- the RISC-V spec fully supports this, though demand is low as there is not yet a lot of legacy 32 bit RISC-V code. Most current RISC-V CPU cores don't support this, though for example the THead C908 does.
There are 100 billion embedded ARM processors in operation now with estimated 230 billion total. RISC-V cant be more than a million so displaced is a bit rich. Someone bought a few. I don't think there is enough of an incentive for adoption for the end user. It's ARMs time now like it or not. RISC-V remains an academic novelty
Link to the open-source processor implementation: https://github.com/OpenXiangShan/XiangShan/tree/nanhu
You can download and simulate it on regular hardware.
I ran a few micro benchmarks it XiangShanV2 (Nanhu, the one in the laptop) and XiangShanV3 the next generation of their implementation:
The Ryzen 1600X is my current desktop and the computer I ran the RTL simulation on.
At the same clock frequency XiangShanV2 is quite competitive with the Zen1 CPU, however it doesn't implement the RISC-V vector extension, so will be a lot slower in any SIMD workloads. The RuyiBook is supposed to clock at 2.5GHz, but there were slides saying it can go up to 2.8GHz, while the 1600X can go up to 3.7GHz.
XiangShanV3 is a lot faster, and does implement the RISC-V vector extension, as well the hypervisor extension. They also target a 3GHz frequency.
Here is a recent presentation of XiangShanV2 micro architectural implementation details: https://raw.githubusercontent.com/OpenXiangShan/XiangShan-do...
There were a few talks at RISC-V Summit Chine regarding XiangShanV3 implementation details. Here is a recording, look at the second Day 2, if the clunky interface works for you: https://www.c114.com.cn/live/t850.html
They also present at this years hotchips in a few days.
Without SIMD is a no-go for most devs.
Yeah, it won't be usable for people who want to optimize SIMD support for RISC-V. However it does have a few extensions we haven't seen in hardware yet, like all scalar cryptography extensions. And it should perform quite similar to the Raspberry Pi 5.
are we really going to recompile all our operating systems, software and embedded firmware and move to RISC-V to save SoC designers royalties to ARM? We have ARM SBCs, accelerators, servers and laptops. Finally a common ISA and we're throwing it out why? because of some virtue signaling from Berkeley. it's a spectacular waste of time and will fail IMO
It's already succeeded in the embedded world, displacing not only a lot of use of Arm, but also pretty much killing off all other custom ISAs that some company engineer invented in order to not have to go through the hassle of licensing a core. All the major FPGA companies now offer a fully-supported RISC-V soft core as well as cores with their proprietary ISAs, and several FPGA companies already offer chips with RISC-V hard cores. In ASICs Synopsys now offers ARC-V and Cadence has some deals in place.
In applications processors chips about to come out in the next 12 months, such as this XiangShan and the SG2380, are getting up into the performance level of 10 year old Zen and Core i5 etc, which is still a perfectly fine performance level for many people and uses.
Linux has been available for RISC-V for many years, a number of distros have 2nd tier support for RISC-V, probably moving to 1st tier soon.
Android is working towards 1st class support for RISC-V, with the desired ISA extensions, fast enough hardware, and full software porting looking to converge into competitive products around 2026-2027.
Arm is NOT a "common ISA". It is proprietary and support can be arbitrarily removed at any time. Since 2023, Arm's highest performance CPU cores have dropped support for the 32 bit ISA(s) even for user programs. That's orphaning an almost 40 year history of 32 bit Arm software, restricting it to being used only on legacy CPUs which will rapidly have much less performance than newer high end CPUs.
At the same time, the low end Arm microcontroller family remains 32 bit only. And the 32 bit and 64 bit ISAs are totally different to each other.
RISC-V vendors on the other hand are happy to license you a 64 bit core with Cortex-M0 or Cortex-M3 size and features. These are often valuable as a control processor in a bigger chip with 64 bit applications processors and >32 bit address space.
In RISC-V the 32 bit and 64 bit ISAs are almost identical and it's very cheap and easy to support 32 bit code on a 64 bit CPU -- the RISC-V spec fully supports this, though demand is low as there is not yet a lot of legacy 32 bit RISC-V code. Most current RISC-V CPU cores don't support this, though for example the THead C908 does.
There are 100 billion embedded ARM processors in operation now with estimated 230 billion total. RISC-V cant be more than a million so displaced is a bit rich. Someone bought a few. I don't think there is enough of an incentive for adoption for the end user. It's ARMs time now like it or not. RISC-V remains an academic novelty
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