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Comment by impossiblefork

1 year ago

But we define the RISC dream as a dream that efficiency, performance and low-cost could be achieved by cores with very small instruction sets?

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impossiblefork

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fanf2  1 year ago

Not small instruction sets, simplified instruction sets. RISC’s main trick is to reduce the number of addressing modes (eg, no memory indirect instructions) and reduce the number of memory operands per instruction to 0 or 1. Use the instruction encoding space for more registers instead.

The surviving CISCs, x86 and z390 are the least CISCy CISCs. The surviving RISCs, arm and power, are the least RISCy RISCs.

RISC V is a weird throwback in some aspects of its instruction set design.

flanked-evergl  1 year ago

If adding more instructions negatively impacts efficiency, performance, cost and complexity, nobody would do it.

  • foldr  1 year ago

    Probably true now, but in ye olde days, some instructions existed primarily to make assembly programming more convenient.

    Assembly programming is a real pain in the RISCiest of RISC architectures, like SPARC. Here's an example from https://www.cs.clemson.edu/course/cpsc827/material/Code%20Ge...:

    • All branches (including the one caused by CALL, below) take place after execution of the following instruction.

    • The position immediately after a branch is the “delay slot” and the instruction found there is the “delay instruction”.

    • If possible, place a useful instruction in the delay slot (one which can safely be done whether or not a conditional branch is taken).

    • If not, place a NOP in the delay slot.

    • Never place any other branch instruction in a delay slot.

    • Do not use SET in a delay slot (only half of it is really there).