Comment by dailykoder
1 day ago
// QEMU UART registers - these addresses are for QEMU's 16550A UART
#define UART_BASE 0x10000000
#define UART_THR (*(volatile char *)(UART_BASE + 0x00)) // Transmit Holding Register
#define UART_RBR (*(volatile char *)(UART_BASE + 0x00)) // Receive Buffer Register
#define UART_LSR (*(volatile char *)(UART_BASE + 0x05)) // Line Status Register
This looks odd. Why are receive and transmit buffer the same and why would you use such a weird offset? Iirc RISC-V allows that, but my gut says I'd still align this to the word size.
> Why are receive and transmit buffer the same?
Backwards compatibility aside, why bother implementing additional register address decoding? Since the host already doesn't need to read THR or write RBR they can be safely combined. Some UARTs call this a DATA register instead.
My sweet summer child… this is backwards compatibility to the I/O register set of NatSemi/Intel's 8250 UART chip…
…from 1978.
https://en.m.wikipedia.org/wiki/8250_UART
The definitions are correct, look up an 16550 datasheet if you want to lose some sanity :)
Oh damn, thanks!