I had a Cyrix 6x86MX and it was good enough for Quake (I played Quake originally on a Pentium-60, and it was fine).
The Quake code was designed to take advantage of the fact that the Pentium could have one integer and one FPU instruction in flight at the same time, thanks to optimizations by an even bigger space-alien wizard than John Carmack -- Michael Abrash. The Cyrix CPUs... couldn't dual-issue instructions like this, so clock-for-clock their performance suffered compared to Intel.
Pentium innovation was FPU that could have many instructions in flight. You would issue 0 cycle free FXCH and keep filling pipeline with new FPU instructions
I had a Cyrix 6x86MX and it was good enough for Quake (I played Quake originally on a Pentium-60, and it was fine).
The Quake code was designed to take advantage of the fact that the Pentium could have one integer and one FPU instruction in flight at the same time, thanks to optimizations by an even bigger space-alien wizard than John Carmack -- Michael Abrash. The Cyrix CPUs... couldn't dual-issue instructions like this, so clock-for-clock their performance suffered compared to Intel.
Pentium innovation was FPU that could have many instructions in flight. You would issue 0 cycle free FXCH and keep filling pipeline with new FPU instructions
https://github.com/id-Software/Quake/blob/bf4ac424ce754894ac...
486, Cyrix, K5 were stopping until previous instruction retires, and even AMD up to late K6-2 revision couldnt do 0 cycle FXCH.
It was alright in Quake, as I recall, but it really didn't cope at all well with Quake 2 and Jedi Knight.