Comment by camel-cdr
2 days ago
There are min/max instructions and zicond: https://github.com/riscvarchive/riscv-zicond/blob/main/zicon...
Most conditional instruxtion sequences are two instructions, cmov is:
czero.eqz rd, rs1, rc
czero.nez rtmp, rs2, rc
or rd, rd, r
Aha, thanks! That seems like a much less appealing proposal to me than a simple mv.eqz/mv.nez. I wonder if there are merits to it that aren't obvious to me.
The reason against a simple conditional move instruction was that this would require a 3R1W integer register file, while the current extension allows for an 2R1W one.
I can definitely see a three-source conditional move being added in conjunction with more 3R1W instructions (see what the scalar efficiency SIG is doing). But my understanding is that the 2R1W design is desired for some of the wide, high-performance designs. (register file size grows quadratically with port count)
Hmm, I guess I had thought you would implement it with a 2R1W register file by just not writing to the register file in the register-file-writing stage of the pipeline when the condition didn't hold, in such simple implementations, same as for jump or store instructions, or those that write to x0. You do have three read dependencies, but without knowing much, I'd guess that's a much smaller problem than a bloated four-port register file.