Comment by kragen

Hmm, I guess I had thought you would implement it with a 2R1W register file by just not writing to the register file in the register-file-writing stage of the pipeline when the condition didn't hold, in such simple implementations, same as for jump or store instructions, or those that write to x0. You do have three read dependencies, but without knowing much, I'd guess that's a much smaller problem than a bloated four-port register file.