Comment by sillywalk
5 months ago
> 768KB I & D cache per core
PA-RISC has mostly always had large L1 caches ( that used to be off-chip), and usually no L2 cache.
I know this bit of trivia, but I don't know the technical reasons/trade-offs for it.
5 months ago
> 768KB I & D cache per core
PA-RISC has mostly always had large L1 caches ( that used to be off-chip), and usually no L2 cache.
I know this bit of trivia, but I don't know the technical reasons/trade-offs for it.
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