Comment by matu3ba
4 months ago
1 Do you have benchmarks for the RISC-V "physical memory protection unit" and/or where can I read more? I'm looking ideally for things like type 1/2 hypervisor or Kernel tutorials for RISC-V to exemplify technical trade-offs. 2 Separation of virtual memory<->security sounds reasonable to offload security eventually to simpler and verified (and ideally eventually synthesized) hypervisors instead of complex Kernels, but I am wondering about capability and debugging limits. 3 The last sentence is very speculative and I dont get how that could be reached.
You can find more in the RISC-V privileged specification[1], section 3.7 I don't have any benchmarks and I think no such generalized benchmarks exists since its a specification and every core brings its own implementation (or none, its optional). With that said, its simple and probably effectively zero overhead, but its also much less capable than what a MMU can do. Its a "protect some firmware against the OS" or "absolute minimum hardware for some memory protection in a cheap MCU", not a competitor to full fat virtual memory.
[1]: https://docs.riscv.org/reference/isa/_attachments/riscv-priv...