Comment by veltas
16 hours ago
RISC-V has always been an ivory tower, with a lot of bad decisions they double down on. Not surprised they're rushing towards this outdated stamp of authority too.
16 hours ago
RISC-V has always been an ivory tower, with a lot of bad decisions they double down on. Not surprised they're rushing towards this outdated stamp of authority too.
>bad decisions they double down on.
Could you elaborate?
No overflow/carry flag impacting safe overflow checking and bignum performance, the whole conditional move history and backpeddling and state of Zicond, the system for describing feature support is needlessly complicated and just a mess for users outside of embedded, the spec is written more like an academic paper than a CPU manual, vector instructions act like they're written for a coprocessor for some reason, bad frame pointer ABI support, etc.