Comment by Aromasin

I'd recommend a pivot to hardware. I'm in the FPGA sector, and vibe coding isn't a thing for the most part, simply because the determinism required doesn't lend itself well to LLMs. It's so incredibly easy to introduce a bug at every single step, and the margin for error depending on volumes is near zero. You're often playing with a single clock cycle of headroom. I've yet to play with a single LLM (Claude Opus 4.5 is my latest trial) that doesn't introduce a massive amount of timing errors. Most semiconductor IP is proprietary, top-level secret, code never leaves the building. The data to build good models just isn't there like it is for software and the open-source ecosystem.

In comms, they have something like a 1:4 ratio of design to validation engineers. Defence is slightly different, as it depends on the company, but generally the tolerance for bugs is zero. Lets not get started on the HF trading folks and their risk appetite!

There's a lot of room for software engineers. Most FPGAs are SoC devices now, running some form of embedded linux doing high-level task management networking. Provided you know enough Verilog to know your way around, you'll be fine. You're also in a space where most engineers I know are preparing to retire in the next 5-10 years, so there will be a panic which will ripple across industries.