Comment by userbinator
10 hours ago
an ordinary part that mapped into 8KB at location >6000->7FFF (the ROM) and another part, that normally held Graphics Programming Language bytecode, mapped into a completely separate “Graphics ROM” address space from >6000->F7FF (the “GROM”).
This reminds me of the NES, which has separate PRG and CHR address spaces, the latter being exclusively for the PPU to display its graphics.
It's not quite the same.
The TI-99/4 has 4k of scratchpad RAM accessible to the CPU. The CPU architecture had no general-purpose registers and had basically only 3 onboad registsrs: the status register, the program counter, and the workspace pointer. The WP pointer to a 32-byte range of RAM that worked like a set of 16 16-bit registers and a subroutine call was a matter of storing the current PC and WP and loading a new pair (a whole new set of registers). The 4k RAM was the equivalent of "the stack" on a modern x86 or Arm CPU.
Programs were stored as bytecode in memory addressable only by the graphics processors (note: not a GPU). Executing a program meant the CPU would write the GROM address to a register on the graphics chips followed by a request to fetch and would then read the byte from another register. It then had to interpret that byte through the ROM.
There were true separate address spaces, not different ranges in the same flat address space like on the NES. The CPU could not address the GROM directly.
I had the Minimem cart that had a line-by-line assembler that let me dump the ROMS. Many hours were spent hand-disassembling the OS for my TI-99/4A.