Comment by drzaiusx11
9 hours ago
That's awesome! I had access to an electron microscope at my last makespace and always wanted to decap a simple chip for reverse engineering. A close friend of mine did that with a SID and recreated it in verilog with good results, which I always found fascinating. Great work on the VIC20 side! And yeah, my VIC20 was never the most stable machine, crashing frequently but I also had a bunch of janky expansion boards attached so ymmv...
I'm also using the knowledge gained from reverse engineering the VIC chip to contribute to a soon to be released VIC chip replacement device called the PIVIC, powered internally by a Pico 2 chip.
Sounds cool! Similar to the SID project, assuming you're also aiming for pin compatibility.
I'm curious why you choose the pico platform over something like TinyFPGA which could be near 100% gate level compatible over a pico with software emulation. I bet the < $3 ICE40 has enough gates?
I haven't really looked at the pico2 yet, maybe it's one of those new hybrid arm+fpga designs and you'd have the best of both worlds?
EDIT: sadly no CPLD/FPGA on the pico2 front, at least according to [1]. Pico2 does add a new RISC-5 core (as a coprocessor? I only skimmed...) So I guess you'd have to do a bunch of timer interrupts to keep things in your emulator clock aligned if you're going pin compatible.
1. https://pip-assets.raspberrypi.com/categories/1214-rp2350/do...