Comment by trynumber9

It does not. For any of the dual CCD parts AMD has ever released for consumers. Even Strix Halo which has higher bandwidth, lower latency interconnect doesn't make a single L3 across CCDs.

It'll probably only happen when they have a singular, large die filled with cache upon which both CCDs are stacked.

Run this test if you're curious: https://github.com/ChipsandCheese/MemoryLatencyTest