Comment by mosaibah
9 hours ago
The gap this closes is real. IceStorm and Apicula gave you open tooling but you were still loading bitstreams onto someone else's closed fabric. Yosys/nextpnr same story. Aegis is the first time the fabric itself is auditable, which matters a lot for anyone building hardware that needs a complete trust chain from RTL down to GDS. The wafer.space + open PDK path makes it actually tapeout-able, not just a simulation exercise. Curious how the LUT4 fabric competes on density against GF180 commercial offerings, that's usually where open implementations get humbling
How do you verify that the fab produces the design authentically? They could create a security vulnerability only they know how to exploit.
Because you can just look into it and see if it's what you sent fof production, and if not and the word gets out you are done as a fab. Fab business is about trust. You also should trust that your design isn't leaked to the competition.
It's very common to xray the dies, especially for debugging. Also common is to etch it layer by layer, take photos and rebuild the circuit schematic, mainly for reverse engineering but I've seen companies doing it to their own dies too.
Things get more blurry at the board level, the combinations of suppliers and service providers are endless.
Is it possible to resolve features on advanced nodes with xray machines? Or the etch and photograph method?
X-ray would be the traditional approach, though quite expensive. IRIS by bunnie is another approach that aims to bring cost way down. Ref https://www.bunniestudios.com/blog/2024/iris-infra-red-in-si...
That’s a nice theory. Fab is one thing, but there are afterwards packaging and testing facilities where silicon can be swapped. I worked for a short time for a military contractor. They don’t X-ray every single chip. They just use it assuming the ordered chip is the one which was delivered by the markings on the package.
How far away are we from being able to run a hobby Linux on something like that, a completely hardware-backdoor-free system?
You can already port over a RISC-V SoC to Aegis. I have not tested that yet but it is something I really want to do.
You can already do that on several Risc-V chips with mmu.