Comment by Neywiny
9 hours ago
While true I do worry that it's mandating a pi 5 for each tile? And who knows how specific it is to the 5. Doesn't seem very open relative to something like a usb superspeed, pcie, or 10gbe. USB could be maybe done with the LIFC-33U depending on I/O limitations. PCIe can be done on various FPGAs in the lattice lineup and others.
If you use PCIe, theoretically you don't need to reverse engineer how they implemented because you're not at the edge of the spec like they are here.
That said, I've thought about doing what they're doing countless times and it is nice to see it would work.
> While true I do worry that it's mandating a pi 5 for each tile? And who knows how specific it is to the 5.
In the multi-tile array it apparently still only needs one Pi [1] as the FPGAs do the heavy lifting.
[1] https://moonrf.com/updates/
correct, one Pi-5 for the MoonRF. The beamforming computation is done digitally "on the fly" in round-robin across the sixty QuadRF boards.