Comment by mazurnification
1 day ago
I believe PSRAM is directly accessible by CPU (there is even cache for PSRAM). Or am I missing something?
1 day ago
I believe PSRAM is directly accessible by CPU (there is even cache for PSRAM). Or am I missing something?
Lerc was referring to driving multiple PSRAM chips from a single Pico with PIO/DMA. The CPU will only work with a single PSRAM chip.
Yes, I was thinking of it more like bank switching.
Although, going back to the start of the thread where the suggestion was adding more RAM to future chips perhaps the request could be for support for multiple channels in the future.
It;s the age old question of parallel Vs serial Vs multi channel serial.