Comment by nippoo
6 hours ago
This is probably a good place to debunk the usual wisdom that "decoupling capacitors must be placed very close to the IC pins". If you're using a solid power plane, rather than routing power through traces (and honestly 4/6 layer boards are cheap enough these days) it really doesn't matter where you place decoupling capacitors for most uses - keep the via traces short or ideally in the pad, and you can put all your decoupling capacitors in one place on the boards a way away from the chip and focus on good routing of your signals. Figure 15 on this paper (and the whole paper!) explains it well: https://scholarsmine.mst.edu/cgi/viewcontent.cgi?article=221...
Loop inductance is what really matters with decoupling. Once you understand that, it becomes really easy to make good decisions. This article explains how you can approximate the inductance for a given layout, so it makes evaluating layouts much simpler. It actually used the data from the paper you referenced in example 3!
https://learnemc.com/estimating-connection-inductance
You can even use mutual inductance of vias improve performance, either by having vias spaced close together and in the right order (https://learnemc.com/decoupling-for-boards-with-widely-space...), or arranging capacitors in alternating or doublet layouts (https://incompliancemag.com/decoupling-capacitor-design-on-p...).
As you say, just having power planes and directly connecting to them is almost always going to be superior to using a trace, despite seeing this all the time, especially in datasheet example layouts. It made sense for 2 layer boards, but not today. Just think, the inductance of the planes is practically zero, and distance to the plane from the components is going to be on the order of 0.2mm, round trip 0.4mm. Is there any way I could place the capacitor 0.4mm away from the pins to achieve an equivalent inductance? And even if you could, you can't add extra vias to lower inductance, and you don't benefit from mutual inductance.
Yeah
The ELI5 for decoupling capacitors is "imagine an energy storage for quick usage"
The ELI(tired EE student) is more like the explanation above
And this concept is ok for most of the 'low speed' circuits
in RF ranges, everything is a capacitor (except when you need one), everything is an inductor (except when you need one) and the intuitive explanations break down and everything looks like dark magic
Well, till it does. Paper talks about frequencies in 200MHz range, not every project can afford solid power planes and putting it next to a chip costs literally nothing. It's like safety helmet, 99.9% of the time it's not needed
Great paper!. Anyonw know whether there are any modern tools/software that can simulate this during design?
For approximative simulation, any SPICE simulator works. You'll need to know your capacitors parasitics and power supply output impedance, find a typical via's impedance, and manually compute traces impedances and board capacitance.
For accurate simulation, the actual board geometry needs to be fed to a simulator that'll compute the actual impedances. Last I checked only Very Expensive Software could do that in a user-friendly way (I had to route a DDR3 bus. I ended up being very cautious so that all traces had the same topology and the same lengths, and cross my fingers. It worked).
If anyone knows of free alternatives for that, I'd be interested to hear about it.