The memory model by itself isn't, however Apple implemented it before Arm released an (incompatible) set of extensions that approach the problem at the instruction level instead of adding an Apple-style global TSO on/off switch in an IMPDEF register [0].
I thought Apple Silicon also has some extra hardware support for handling x86 flags emulation for Rosetta. But perhaps I’m remembering that incorrectly.
The memory model by itself isn't, however Apple implemented it before Arm released an (incompatible) set of extensions that approach the problem at the instruction level instead of adding an Apple-style global TSO on/off switch in an IMPDEF register [0].
[0] https://lkml.org/lkml/2024/4/10/1531
I stand corrected!
I thought Apple Silicon also has some extra hardware support for handling x86 flags emulation for Rosetta. But perhaps I’m remembering that incorrectly.