Comment by imtringued

The concept of alignment isn't a hardware defect, maybe limitation, but the reason why alignment is a thing has to do with the fact that in chip interconnects transfer blocks. You cannot perform misaligned memory accesses against RAM.

A similar limitation exists when peforming accesses against the cache, but at a much finer granularity.

For bytes, the alignment restriction obviously exists in the 8 bit level. You have one output byte and 64 multiplexer inputs.

If you scale this up to 8 bytes, you will need a lot of 64 Input multiplexers.

But even if you can take the silicon area hit, there is the problem of crossing cache lines and pages.

In the end, you cannot divide memory into blocks and allow primitives to cross those blocks without requesting both blocks at the same time. That's an inefficient waste of resources so why support the wasteful usecase in the first place?