Comment by buran77
1 day ago
> logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM’s 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible.
Continuing the well established trend of making bold claims about physical dimensions that have nothing to do with any of the structures in the chip, and the name scales better than the tech.
What they actually deliver is a "nanostack architecture" built with ~5nm features that according to them is comparable to a hypothetical real sub-1nm chip.
It's an impressive achievement nonetheless but it looks like the industry has a few too many marketers.
As it can be seen from the photos, horizontally the features are much bigger than 5 nm.
For silicon, the gate length of a FET has a lower limit somewhere between 10 nm and 15 nm.
The current CMOS manufacturing processes have not reached the limit yet. For making smaller transistors, a transition to other semiconductor materials will be necessary.
The vertical thicknesses of various layers may be of only a few nanometers or even of a fraction of a nanometer, but that does not matter directly for the circuit density.
The supposed node size refers to horizontal dimensions, not to vertical dimensions.
Vertical dimensions of around 1 nanometer or less could be achieved already many decades ago, because they depend on growth speed and on time, not on lithography, like the horizontal dimensions.
The industry should have stopped decades ago to talk about the "size" but they should have characterized a CMOS process by its density, e.g. in logic gates per square mm.
However, an actual concrete number would be disliked by marketing, because they could no longer claim that their "1 nm" process is better than the "2 nm" process of another vendor, if their density is not really better.
>The vertical thicknesses of various layers may be of only a few nanometers or even of a fraction of a nanometer
We should flip the transistors sideways then!
Shades of
"You can't go to the sun! You'll burn alive!"
"Duh! That's why we're going at night!"
Just get better marketers to say your 2nm process has more gates per sqmm than your competition 1nm process.
Exactly. WatsonX AI quantum angstroms for e-business.
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The scale bar on the far right "photo" (micrograph?) doesn't make sense. It is only slightly less than half the scale bar on the middle photo (10 nm), but the image is clearly scaled up by much more than 2x. Individual silicon atoms are circled in the right photo, but the covalent radius of silicon is about 0.11 nm, so they should be much smaller if the scale bar is accurate.
The scale bar also got about 50% longer, which would imply a 3x zoom. That also seems about right based on the relative feature sizes. Same thing happened between the first and second image.
Marketing scams has been the norm for the silicon industry for a big decade.
How would you fix that? This is a global scam. Big Markets regulating them: that would have to be the USA and EU.
Unlike marketing terms, "nm density" is actually useful measure.
It describes density measure where you can compare it to planar transistors from the 28-nanometer (28 nm) node around 2010 to 2011 and before. A "0.7 nm" node has equivalent transistor density as if we could have shrunk standard flat transistor node down to 0.7 nanometers.
Why not use something absolute, like nand-gates per volume?
Transistor density in units of MTr/mm. (Million Transistors per square mm) is also used. The formula is
MTr/mm = 0.6×(NAND2 Tr Count)/(NAND2 Cell Area) + 0.4×(Scan Flip Flop Tr Count)/(Scan Flip Flop Cell Area)
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I am not a chip designer, doesn't area matter way more than volume? Vertical space is basically free; it's horizontal space that is at a huge premium.
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Why is density any bit important? All I care about is the price per transistor, and the power usage(mostly gate charge and leakage current?).
Density does directly scale with both of those in the form of more chips per die (=> lower cost) and smaller capacitance (=> less dynamic power dissipation).
If you want to reduce "effectiveness" of some process down to a single number, then density is far from the worst metric to pick.
Why is that all you care about? Stepping down a node gets you dramatically improved timing and design feasibility. The reduced density means you can pack the same design into less area. Your most challenging timing paths now have to traverse a shorter distance, and you can fit more of them relative to certain node-size invariant structures
isn't density a way to lower both the price and energy dissipation (so better heat management & energy efficiency)?
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Yeah, the actual sizes are right there in the pictures, and never < 1 nm.
Density is mass per volume so how are you comparing it to a planar transistor? Your units don't even match.
All "density" means is that it's a quotient; I use spectral densities daily and that's "count per Hertz" which weirdly enough works out in normal units to be seconds.
Not all densities is mass per volume. eg. population density.
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density is quantity per unit measure.
mass per volume is one example.
Density is this reply.
https://en.wikipedia.org/wiki/Transistor_count#Transistor_de...
It's been decades since published node sizes had any connection to actual feature size. Sadly this is just how it works in the semiconductor industry now.
We've already been through years of "7nm isn't actually 7nm" across different fabs - completely different measurement conventions, none corresponding to real feature sizes. Now sub-1nm? If it is real then at that scale we're probably in the several atom width territory.
Who started it?
https://www.eejournal.com/article/no-more-nanometers/
Sometime around 2011 when Intel named their process node 22nm which the gate length was 26nm
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Smart money would be on the first person who realized that the expertise required to understand the technical details had grown beyond that possessed by 51%+ of stock investing (trading?) population as weighted by transaction volume.
My read on it was that they are trying to imply a transistor density (in a 2D plane sense) that is comparable to a 1nm process? But they achieve that through stacking (3D, not 2D) since the features aren't actually anywhere near 1nm?
If they're adding a dimension, the marketing should reflect that.
I know they won't go for an anything that makes as much sense as 5nm3, so I vote for "1nm hyper space"
Should population density in cities also be measured in hab/km³ rather than hab/km²?
We are used to stacking people vertically in cities.
“TeraThread”
Correction: it’s not stacking. They do things like FinFET (turning the gates in the third dimension) and gate-all-around which increases the density of transistors per unit area. But they don’t have layers of transistors. At least in the logic and analog processes.
What industry doesn't have a few too many marketers? Take everything with a grain of salt.
yeah, where on the pictures is the 0.7nm feature? The linespacing is around 5nm. Is it the white line which is 0.7nm?
I really can't see where the 0.7nm is coming from. The white line looks like it's just an edge of a feature that is "15 rows of silicon atoms", which by some quick arithmetic on Wolfram Alpha has to be AT LEAST ~1.6nm, and the way the rows of atoms appear to be packed in that image and by the provided scale, it seems to be significantly more. Using the white line as a meaningful measurement seems to me to be more misleading than any other interpretation here.
It's the equivalent performance of a 0.7 nm planar transistor. It's not about the feature size.
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Better metrics are transistors/mm^2, performance/watt, and raw performance, since at this point "nm" is fluff and easily game-able.
Different companies measure it differently too. This was a while ago, but I remember reading that Intel 10nm was more or less close to TSMC 7nm. I'm sure this is still true to varying degrees.
Comparing nodes across foundries is a kind of a coin toss. At least, from the name. You actually need to go into the specifics of the pdk and process to understand what features there are. Can’t rely on the name for anything.
I believe it could be a stepping stone to significantly higher density in the future.
only a matter of time before some marketer figures out they can get promoted by branding a generation of chips 0nm
On the otherhand, no investor really cares what it's called, they just need to know it's next gen.
> Continuing the well established trend of making bold claims about physical dimensions that have nothing to do with any of the structures in the chip, and the name scales better than the tech.
We care about PPA (power, performance, area) and not how large or not-large features actually are. Comparing gate lengths between a 1980s planar transistor and a 2010s 3D FinFET or GAA transistor is obviously nonsense, the relatively aligned node names of the industry actually do make sense as a shortcut here.
You have to admit it's getting progressively sillier though.