← Back to context Comment by jayd16 1 day ago Why not use something absolute, like nand-gates per volume? 4 comments jayd16 Reply u1hcw9nx 1 day ago Transistor density in units of MTr/mm. (Million Transistors per square mm) is also used. The formula isMTr/mm = 0.6×(NAND2 Tr Count)/(NAND2 Cell Area) + 0.4×(Scan Flip Flop Tr Count)/(Scan Flip Flop Cell Area) jayd16 6 hours ago Why do you think it's not commonly used? mikepurvis 1 day ago I am not a chip designer, doesn't area matter way more than volume? Vertical space is basically free; it's horizontal space that is at a huge premium. Intralexical 17 hours ago Plus heat dissipation is a limiting factor, which scales with area.
u1hcw9nx 1 day ago Transistor density in units of MTr/mm. (Million Transistors per square mm) is also used. The formula isMTr/mm = 0.6×(NAND2 Tr Count)/(NAND2 Cell Area) + 0.4×(Scan Flip Flop Tr Count)/(Scan Flip Flop Cell Area) jayd16 6 hours ago Why do you think it's not commonly used?
mikepurvis 1 day ago I am not a chip designer, doesn't area matter way more than volume? Vertical space is basically free; it's horizontal space that is at a huge premium. Intralexical 17 hours ago Plus heat dissipation is a limiting factor, which scales with area.
Transistor density in units of MTr/mm. (Million Transistors per square mm) is also used. The formula is
MTr/mm = 0.6×(NAND2 Tr Count)/(NAND2 Cell Area) + 0.4×(Scan Flip Flop Tr Count)/(Scan Flip Flop Cell Area)
Why do you think it's not commonly used?
I am not a chip designer, doesn't area matter way more than volume? Vertical space is basically free; it's horizontal space that is at a huge premium.
Plus heat dissipation is a limiting factor, which scales with area.