Comment by tancop

all production ics have a flat layout with 3d transistors. the physical limit is how close can the features on one wafer get before theres too much tunneling.

there is a clear way forward with wafer stacking instead of shrinking layouts but so far we only have amd v-cache style asymmetric designs with memory stacked on top of compute. for a fully connected stack that acts like a single chip you need insane precision to align the wafers and a way to remove heat from the middle so the chips dont fry themselves.

if someone finds a way to stack cpu cores without thermal issues that will be a real revolution. huawei might be close with their logic folding but nobody knows if it really works and what the heat problems are like.