Comment by Taniwha
14 hours ago
Thing is capability machines (like this and the 432 and lots of research machines) were very much the thing at the time - cutting edge even. The research literature was full of them. I did a paper design at the time.
What ate them up was "what can you fit all on a chip with not many pins", followed by "what can you fit along with a cache on a chip with more pins", things move so much faster if everything's on the same die.
Tagged architectures are old, Burroughs mainframes had them back in the 70s along with rudimentary hardware objects (pageable even)
The end of the article seems to admit all of what you say but then suggest it is time to revisit; do you think that’s valid or no?
I'm in 2 minds, I'm strongly in the RISC camp these days, I know how hard it is to build a truly performant CPU and think that simpler is better as far as ISAs go. Adding segmentation hardware into the addressing path means more clocks and makes it's harder to detect loads/stores that interfere with each other (all load/stores have to block each other until the addressing/tlb lookup has been done ie detecting aliasing ).
A true capability architecture needs separate register files for pointers and data with protections enforced when the address registers are loaded/stored, it's a step away from our models of linear address spaces that many of the languages we use today are based on. And any new CPU that requires everyone to learn a new language is probably a non-starter as a mainstream CPU
If only the LLMs have to learn the new language then maybe it can be a starter?
Can you expand on your paper computer? It sounds fascinating.
It was more than 40 years ago, before I had the skills to build chips, I'm afraid I've kept nothing of that design