Comment by Taniwha

I'm in 2 minds, I'm strongly in the RISC camp these days, I know how hard it is to build a truly performant CPU and think that simpler is better as far as ISAs go. Adding segmentation hardware into the addressing path means more clocks and makes it's harder to detect loads/stores that interfere with each other (all load/stores have to block each other until the addressing/tlb lookup has been done ie detecting aliasing ).

A true capability architecture needs separate register files for pointers and data with protections enforced when the address registers are loaded/stored, it's a step away from our models of linear address spaces that many of the languages we use today are based on. And any new CPU that requires everyone to learn a new language is probably a non-starter as a mainstream CPU