Comment by doctoboggan
21 hours ago
I think the SotA is moving too fast for the production timelines of an ASIC, wouldn't you think? People are just now coming out with LLAMA ASICS but who would want to use LLAMA? Or I guess you are arguing that the models _now_ will be durably useful enough to commit the time to creating the ASIC?
Objectively, the current frontier-ish models will be useful for some time. Imagine the zombie apocolypse hits, recedes, and you need to rebuild society. An offline copy of Fable or even Opus would be a nice thing to have.
Subjectively, it's hard to say if people will pay for "a model from 18 months ago, but REALLY FAST AND CHEAP"
The speed difference suggests some use cases that might narrow the performance gap. With a > 50x performance delta you have some headroom to play with.
You can do many many fast iterations of ye olde "Ralph loops." You can also jack up the reasoning/effort level. And you could probably do some combination of both, while still running really fast ie 10x the number of iterations at 2x reasoning/effort.
So I think a hypothetical "50x faster Opus 4.8, but burned into ASICs" could be pretty competitive against the frontier models from 2027, 2028, 2029, and maybe beyond?
I dream of some kind of "adjustable" ASIC layers, that have the most "computation demanding" layers as ASICs plus a bunch of configurable R+W circuits (FPGAs?) that can be written to upgrade the models to some extent.
What's fascinating is that we are pushing the state of the art of hardware at this point.