Don't forget the 128 bit vector ISA with 32 registers, supporting up to 64 bit int and FP, and with LMUL=8 you can process 1024 bits with a single instruction (at 3 cycles per 128 bits for most operations). Fully supported by GCC and CLANG (xTHeadVector) and compatible with RVV 1.0 with just a command line switch if you use the C intrinsic functions. (a lot of code working on 8 bit elements is binary compatible with RVV 1.0 too e.g. typical memcpy(), memset(), memcmp(), strlen(), strcpy(), strcmp())
When I bought my 64 MB Duo they were $3!
Then for a long time they were $5 for the 64 MB, $7 for the 256 MB, and $10 for the 512 MB.
Sadly, like everything else, they've gone up considerably this year.
You can buy sub-$0.50 microcontrollers. But even at $5, I don't know why you'd want to run models on them, it's an environment constrained to the point of being useless for this task.
And I hope it stays that way, I don't want MCU shortages...
Many artificial environments are useless to tasks they were not designed for until somebody experiments, tests, redesigns, and iterates.
I'll give a specific example apropos of TFA. Computer vision models were never run on MCUs because they were constrained to the point of being useless for this task, but then someone tried the impractical, and now it's trivial[1]
Regarding MCU shortages, you should be worried about the supply chain, but I don't see the impact really being from running LLMs on ESP-32s, of all things.
Fun and learning is a really good reason. It also reminds me of the damascene: trying to achieve something that doesn't feel possible, and working through all the extreme resource-constrained engineering limits.
I think most of my embedded projects aren't that useful, but they've taught me a lot.
How is it useless? If it has an NPU it is literally built to run models.
You're just extremely biased in what you consider to be a useful ML model. For example, for some strange reason you think only LLMs exist. The model must be as big as possible or else it is pointless.
Training custom non-LLM models for specific tasks so they run on a resource constrained device? You must be insane.
There's a neat project out there that can read your water meter into home assistant using an ESP32+camera+computer vision. I imagine a small TPU like this could be very useful for similar projects. More compute means higher resolutions and more reliability.
I think that is pretty ungenerous. Before ARM, ISAs were not a commodity, and there were only closed, proprietary implementations of them (usually from a single vendor). Arm licensing its IP and actual designs was hugely beneficial for the broader ecosystem and led to their prevalence in the embedded space. The toolchain and software network effect made it a no-brainer to either reach for a completed Arm design, contract a customized one, or build your own.
The arm experiment ran its course though; the power one vendor had in the marketplace started to be abused for the benefit of the IP holder and detriment to others. Now RISC-V is going one step further with a completely open ISA and also completely open designs. This is an excellent development in the nick of time.
I wonder how Apple feels about arm64 and RISC-V now. They could have probably bought ARM at any point but maybe never considered it to avoid anti-monopoly blowback.
My goto for what I hate about modern tech is toothbrushes having Bluetooth and needing apps.
Not that I hate all modern tech but if it needs an app I probably will.
This is a really neat use of the per-layer embedding trick. It's also worth noting that there viable TTS models that are ~20-30M param, so it might mean you can have a ESP32 with no network access read stuff out to you in near real time!
One of the things I have been wanting to try for a while now is something like this with a layer per MCU. I have some crazy ideas with RP2350's talking to each other with dedicated lines fed by PIO going through a combination of interpolators and dual multiply instructions.
PSRAM, Flash, and even SD cards may not have the best bandwidth individually, but they can reach quite impressive rates when you have a shitton of them running all at the same time.
The large scale dedicated hardware systems will still have the edge for performance per watt, but the low entry level and slow incline does make these things quite appealing.
That's incredible. Sure, not practical for most applications, but if you really want a local top tier model, you can run it on anything as long as you are patient.
As someone with a healthy amount of RAM, but just a 16GB GPU, I am wondering what kind of work I could queue up for overnight runs. I thought the best models were fully out of reach, but the 128GB CPU only test had a 1.8 tokens/second. While not speedy, you could probably do something with that given extensive coffee breaks. This speed simulator[0] demos what it looks like.
So while SSD streaming is interesting I'm not sure it's exactly the same thing as the per-layer embedding that is being utilized in tandem with streaming here. To utilize per-layer embedding, it would have had to be trained that way, which GLM 5.2 was not.
more interesting would be using some kind of FPGA to logic glue each RAM socket interface bitplane to a hard drive (so a collection of hard drives with ridiculous collective bandwidth). Perhaps a single RAM socket contains actual RAM and the linux kernel would have to be modified to only use the real RAM memory region for OS and inference software, with the inference software rewritten to stream LLM weights deterministically from the hijacked RAM slot physical memory regions. Obviously the FPGA can't truly achieve the CAS latencies over the HDD (unless the HDD firmware was rewritten so it can predict the next deterministic token sufficiently in advance to cache the result and stream it just in time to FPGA then "RAM" socket...) but even if the HDD firmware can't be reprogrammed for some reason, the FPGA knows what memory address will be deterministically fetched next, so it can make the requests to the parallel array of HDD's ahead of time.
My guess is because the ESP32's flash is only ~1/4 the bandwidth of the internal SRAM. If you do this on a more powerful system not only is the gap much wider but you also have much more compute you need to keep fed with bandwidth to be efficient.
It's also mapped into the address space so there's very little extra latency in grabbing the embedding as opposed to something like nvme that will have to setup a command list, submit it to the drive's microcontroller, wait for the op to be processed, etc.
If you want to do this at the $1 price point, you can on RP2350, albeit with some limitations. In particular, it maxes out at full speed (12Mbps). The trick is to use the on-chip USB peripheral for one, and connect the other to GPIO pins backed by PIO.
This works today with tinyusb and pico-pio-usb, but I'm also playing with a Rust port which I'm hoping will have higher performance.
$8 ish gets you an ESP32-S3 board with PSRAM, flash, and two USB-C ports. The PSRAM and flash are specifically used for this LLM project. I can't find anything like that with the RP2350 for $1.
It's quite sad people collectively behave as if leaderboards have served their time.
In the small parameter regime there is no room for benchmaxxing, so instead of leaderboards becoming useless, their utility was merely reduced to establishing ever smaller models with similar performance on the benchmarks, forcing compression or redundancy to be recognized and eliminated at the modeling level.
Pretty incredible performance for the footprint - really interested to see what could be done on slightly more powerful SBCs like some that have been mentioned in this thread.
It's crazy what $5 can buy you in a microcontroller these days. Have a look at these Milk-V boards:
https://milkv.io
The duo has up to 256MB of memory, and a 1TOPS@INT8 TPU. They run Linux and are $5. I bought 5!
Don't forget the 128 bit vector ISA with 32 registers, supporting up to 64 bit int and FP, and with LMUL=8 you can process 1024 bits with a single instruction (at 3 cycles per 128 bits for most operations). Fully supported by GCC and CLANG (xTHeadVector) and compatible with RVV 1.0 with just a command line switch if you use the C intrinsic functions. (a lot of code working on 8 bit elements is binary compatible with RVV 1.0 too e.g. typical memcpy(), memset(), memcmp(), strlen(), strcpy(), strcmp())
When I bought my 64 MB Duo they were $3!
Then for a long time they were $5 for the 64 MB, $7 for the 256 MB, and $10 for the 512 MB.
Sadly, like everything else, they've gone up considerably this year.
https://arace.tech/products/milk-v-duo
https://arace.tech/products/milkv-duo-s
Meaning, minus possible required bug fixes, all the frontend languages supported on a full instal of either GCC or LLVM.
3 replies →
You can buy sub-$0.50 microcontrollers. But even at $5, I don't know why you'd want to run models on them, it's an environment constrained to the point of being useless for this task.
And I hope it stays that way, I don't want MCU shortages...
Many artificial environments are useless to tasks they were not designed for until somebody experiments, tests, redesigns, and iterates.
I'll give a specific example apropos of TFA. Computer vision models were never run on MCUs because they were constrained to the point of being useless for this task, but then someone tried the impractical, and now it's trivial[1]
Regarding MCU shortages, you should be worried about the supply chain, but I don't see the impact really being from running LLMs on ESP-32s, of all things.
[1]: https://github.com/espressif/esp-vision
Fun and learning is a really good reason. It also reminds me of the damascene: trying to achieve something that doesn't feel possible, and working through all the extreme resource-constrained engineering limits.
I think most of my embedded projects aren't that useful, but they've taught me a lot.
3 replies →
How is it useless? If it has an NPU it is literally built to run models.
You're just extremely biased in what you consider to be a useful ML model. For example, for some strange reason you think only LLMs exist. The model must be as big as possible or else it is pointless.
Training custom non-LLM models for specific tasks so they run on a resource constrained device? You must be insane.
There's a neat project out there that can read your water meter into home assistant using an ESP32+camera+computer vision. I imagine a small TPU like this could be very useful for similar projects. More compute means higher resolutions and more reliability.
2 replies →
I want to run music models on the Milk-V and have them jam in realtime with me.
isn't floor price 0.10$ for last couple years?
6 replies →
I bought 5!
What are you going to do with 120 of them?
A compute cluster for generating bad math jokes.
Which is why folks should stop thinking that coding in Assembly, or C is the only way, as if microcontrollers were stuck in the 80s hardware.
Heck, that one would have no issue running Xerox PARC OSes.
Naturally there are still use cases were a PIC with 4KB would be the best option, but lets not behave as if there isn't anything better in most cases.
It really puts into perspective how much of a leech ARM has been on the entire industry. What being a monopoly does to a mfer.
I think that is pretty ungenerous. Before ARM, ISAs were not a commodity, and there were only closed, proprietary implementations of them (usually from a single vendor). Arm licensing its IP and actual designs was hugely beneficial for the broader ecosystem and led to their prevalence in the embedded space. The toolchain and software network effect made it a no-brainer to either reach for a completed Arm design, contract a customized one, or build your own.
The arm experiment ran its course though; the power one vendor had in the marketplace started to be abused for the benefit of the IP holder and detriment to others. Now RISC-V is going one step further with a completely open ISA and also completely open designs. This is an excellent development in the nick of time.
I wonder how Apple feels about arm64 and RISC-V now. They could have probably bought ARM at any point but maybe never considered it to avoid anti-monopoly blowback.
Sure, because the jungle of 8, 16 and 32 bit microcontrollers stuck on 1980's mindset was so much better.
Also you can reach out to ESP32 as alternative, plenty of maker projects using them.
Voice-to-Text and Text-to-Voice models are approaching that size. I wonder how close we are to getting small devices that can chat with us.
Imagine a world where your toothbrush could give you tips about dental hygiene - or advertise toothpaste. What a time to be alive!
> tips about dental hygiene
They already can. Philips' higher end models have Bluetooth connections and provide feedback through the app.
> advertise toothpaste
God please no. I don't want to have to look for an adblocker for a toothbrush AI.
My goto for what I hate about modern tech is toothbrushes having Bluetooth and needing apps. Not that I hate all modern tech but if it needs an app I probably will.
1 reply →
And this is why I am extremely bullish on Apple.
PLEASE DRINK A VERIFICATION CAN
This is a really neat use of the per-layer embedding trick. It's also worth noting that there viable TTS models that are ~20-30M param, so it might mean you can have a ESP32 with no network access read stuff out to you in near real time!
One of the things I have been wanting to try for a while now is something like this with a layer per MCU. I have some crazy ideas with RP2350's talking to each other with dedicated lines fed by PIO going through a combination of interpolators and dual multiply instructions.
PSRAM, Flash, and even SD cards may not have the best bandwidth individually, but they can reach quite impressive rates when you have a shitton of them running all at the same time.
The large scale dedicated hardware systems will still have the edge for performance per watt, but the low entry level and slow incline does make these things quite appealing.
Run the numbers before you waste time here. I doubt this will work.
2 replies →
Wouldn't a layer per MCU be heavily bandwidth constrained?
1 reply →
Why can't this scale to run much larger models on CPU backed by flash with good access patterns?
Someone did this exact thing recently, but running GLM-5.2 with something like 16GB of DRAM, a standard desktop CPU and nVME SSD.
I think they got something like 10 _seconds per token_ (not tokens per second).
EDIT: it was 25GB of ram and up to 20 seconds per token! https://github.com/JustVugg/colibri
That's incredible. Sure, not practical for most applications, but if you really want a local top tier model, you can run it on anything as long as you are patient.
As someone with a healthy amount of RAM, but just a 16GB GPU, I am wondering what kind of work I could queue up for overnight runs. I thought the best models were fully out of reach, but the 128GB CPU only test had a 1.8 tokens/second. While not speedy, you could probably do something with that given extensive coffee breaks. This speed simulator[0] demos what it looks like.
[0] https://shir-man.com/tokens-per-second/?speed=1.8
1 reply →
So while SSD streaming is interesting I'm not sure it's exactly the same thing as the per-layer embedding that is being utilized in tandem with streaming here. To utilize per-layer embedding, it would have had to be trained that way, which GLM 5.2 was not.
more interesting would be using some kind of FPGA to logic glue each RAM socket interface bitplane to a hard drive (so a collection of hard drives with ridiculous collective bandwidth). Perhaps a single RAM socket contains actual RAM and the linux kernel would have to be modified to only use the real RAM memory region for OS and inference software, with the inference software rewritten to stream LLM weights deterministically from the hijacked RAM slot physical memory regions. Obviously the FPGA can't truly achieve the CAS latencies over the HDD (unless the HDD firmware was rewritten so it can predict the next deterministic token sufficiently in advance to cache the result and stream it just in time to FPGA then "RAM" socket...) but even if the HDD firmware can't be reprogrammed for some reason, the FPGA knows what memory address will be deterministically fetched next, so it can make the requests to the parallel array of HDD's ahead of time.
Rig with 6x RTX 5090. I would not say it is RAM only
1 reply →
My guess is because the ESP32's flash is only ~1/4 the bandwidth of the internal SRAM. If you do this on a more powerful system not only is the gap much wider but you also have much more compute you need to keep fed with bandwidth to be efficient.
It's also mapped into the address space so there's very little extra latency in grabbing the embedding as opposed to something like nvme that will have to setup a command list, submit it to the drive's microcontroller, wait for the op to be processed, etc.
>esp32-s3
This microcontroller is a beast, currently using it to do dev work on a pi4.
Having two usb ports with one otg lets you do some neat things that would cost $100+ otherwise
If you want to do this at the $1 price point, you can on RP2350, albeit with some limitations. In particular, it maxes out at full speed (12Mbps). The trick is to use the on-chip USB peripheral for one, and connect the other to GPIO pins backed by PIO.
This works today with tinyusb and pico-pio-usb, but I'm also playing with a Rust port which I'm hoping will have higher performance.
$8 ish gets you an ESP32-S3 board with PSRAM, flash, and two USB-C ports. The PSRAM and flash are specifically used for this LLM project. I can't find anything like that with the RP2350 for $1.
1 reply →
While running LLM on tiny device is awesome, I'm more impressed by whatever training has produced the weights
It's quite sad people collectively behave as if leaderboards have served their time.
In the small parameter regime there is no room for benchmaxxing, so instead of leaderboards becoming useless, their utility was merely reduced to establishing ever smaller models with similar performance on the benchmarks, forcing compression or redundancy to be recognized and eliminated at the modeling level.
i don't care about microcontroller, what is the decent option to have local llm in my raspi4 that does not take 30 seconds to answer?
Run a smaller LLM. It won't be as smart but the one shown here isn't either.
Pretty incredible performance for the footprint - really interested to see what could be done on slightly more powerful SBCs like some that have been mentioned in this thread.
This is a really cool project. Thanks for sharing!
9.7 tokens/sec actually seems like a lot! That’s fun!
How accurate is this quantized model?
Finally, an LLM that can run on my i5
Super cool, thank you for sharing!
How lovely j
Wont this wear out the flash memory quickly? I wonder hiw many read cycles can it survive
Reads are effectively infinite. I'm not aware of any upper limit shorter than "end of the universe" timescales.
Flash wears out from writing and the answer is in the tens to hundreds of thousands of writes per cell.
https://docs.espressif.com/projects/esp-idf/en/stable/esp32/...
It's write and/or erase cycles that cause wear.
[flagged]
[dead]
[dead]