Comment by brucehoult
2 days ago
Don't forget the 128 bit vector ISA with 32 registers, supporting up to 64 bit int and FP, and with LMUL=8 you can process 1024 bits with a single instruction (at 3 cycles per 128 bits for most operations). Fully supported by GCC and CLANG (xTHeadVector) and compatible with RVV 1.0 with just a command line switch if you use the C intrinsic functions. (a lot of code working on 8 bit elements is binary compatible with RVV 1.0 too e.g. typical memcpy(), memset(), memcmp(), strlen(), strcpy(), strcmp())
When I bought my 64 MB Duo they were $3!
Then for a long time they were $5 for the 64 MB, $7 for the 256 MB, and $10 for the 512 MB.
Sadly, like everything else, they've gone up considerably this year.
Meaning, minus possible required bug fixes, all the frontend languages supported on a full instal of either GCC or LLVM.
The wild thing is that this SoC is a heterogenous compute device. It has three different kinds of cores: a pretty beefy arm64 core and two different RISC-V cores: a 1Ghz one for running Linux and a 700Mhz one dedicated to running a real-time operating system. The arm64 core can also run its own OS.
Also a user-programmable 300 MHz 8051 (8 bit) primarily there to manage timers and interrupts and wake up the big 64 bit cores.
Note that the application-processor 1 GHz C906 and Arm A53 are either/or, you can't run both at the same time — similar to the Arm M33 and RISC-V Hazard3 core pairs on the Raspberry Pi RP2350.
I haven't noticed it, rather cool!