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Comment by jrflo

3 hours ago

Burning the weights into silicon would be many orders of magnitude increase, not just 10x. It's kind of crazy that this hockey stick the AI hype bros talk about seems more and more every day like it might be real

https://taalas.com/ has done it already for a wildly obsolete model. 14000 tokens per second.

https://chatjimmy.ai/ is their interactive. Tiny context, very dumb, but absurdly fast. Imagine this as a tool call for claude code for trivial changes - the tool call from the harness takes longer than the execution.

  • Wow. This is absolutely wild. I didn't expect that.

    If we get to anywhere near this speed for the equivalent of the current models... I don't even know what to think about that future.

    • Speed is the metric I'm currently most interested in. The models are smart enough.

      Once speed significantly increases I think we're going to see some interesting downstream effects. The three things I currently spend the most time waiting on are LLM API requests, Rust compile times, and nix derivations. As AI latency approaches zero I think we're going to start taking a hard look at whether slow-compiling languages are adding enough value over Golang, Typescript, or even dynamic languages to be worth the slowdown.

  • Holy crap, I was not prepared for how fast it responded. I just wrote "Just wanted to see how fast you are! Can you write me a quick story about a tiger who lives inside a block of cheese the size of a house?"

    I pressed Enter, and the response was instant.

    > Generated in 0.037s • 14,205 tok/s

    This is unbelievable.

    • "Stochastic gradient descent algorithm in Haskel"

      "LMS algorithm in bash"

      Just barfed it up lol.

      Amazing.

    • Just wow, I made a similar request. Result: Generated in 0.042s • 14,201 tok/s

      This is crazy.

    • For what its worth the frontier lab models can surely be a lot faster if they wanted them to be but theyre supply constrained so theyre doing stuff like multi tenancy. Since you cant self host them no one outside the labs really knows speed as a solo tenant

      1 reply →

And don't underestimate how much money Google, Microsoft, Amazon and Meta still have to spend on this tech.

Blocking Fable for sure made it very politicl a lot sooner than i expected it to happen.

and because China already has massive problems of getting access, they are pushing it on hardware too like what Huawai did without EUV.

It seems China is already able to do DUV a lot sooner than others expected.

  • > It seems China is already able to do DUV a lot sooner than others expected.

    That's the media and in particular US KOLs of all sorts driving the wrong impression of China and other places. China and many other places for example have fast public transport that the US doesn't and can't even imagine today. They're not behind.

    China's DUV still isn't that production grade (mass produce-able) so don't get that hyped up the wrong way (in a different direction).

    The whole China-is-behind with tech and in particular semi wasn't that they can't. The truth is they spent decades in internal politics and corruption. That all got solved with the bans, so thank the bans! Jensen even said the bans were bad.

Yep it will be ASICs and DSPs all over again. Orders of magnitude changes.

  • So which shovels companies are the ones to watch for burnt in silicon models ?

    • Imagine the price of a $9 million NVL72 dropped to about $100, used 4 orders of magnitude less power, was the size of ARM cpu, be bundled with pretty much any electronic device, and ran as fast a frontier AI is today.

      That's about how disrupting DSPs were to the industries they arose out of (over a very long time frame).

      How would that disrupt the industry?

Not an expert on this but wouldn’t this be possible with something similar to an FPGA?

  • My understanding is that for FPGA the issue is either it eats all your gates on internal memory if you interleave, or it takes forever to load everything between the SRAM on the board and the actual FPGA component over a bus, last time I looked into it.

  • Weights can be baked into silicone or programmed into hardware ala FPGA, but the context will always be dynamic.

    High speed SRAM is where the $$$ is

What does that mean though? Like some kind of a ROM memory ?

  • Stacked ROM can, in theory, be a lot denser than anything that depends on a capacitor and refresh cycle.

    I don't think it would be that difficult to manufacture compared to other process tech. HBM is really hard to do compared to other memory types.