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Comment by Melatonic

8 hours ago

The Taalas chips are not physically small. And part of their secret (if you look at the design) is just locating a bunch of memory soldered on the edges ( I belive higher amounts of SRAM ? )

Baking the base models on to ROM makes a lot of economic sense. SRAM for the KV cache & fine-tunes, not so much. Sure you’d get incredible speeds but it’s not scalable from a die-size or cost perspective.

Rather base model on ROM + KV cache on DRAM is much more scalable. Also this would work great for edge devices that have a 2-5 year lifecycle.

  • We also have ReRAM (Analog Computing), which also holds a promising future given its efficiency and low power. Though ReRAM of larger size is still a research area.

  • Baking the base models on to ROM makes a lot of economic sense.

    Less so for consumers though, because it'd mean the phone is out of date in 3 months when a better model comes along.

    • I don’t think average user _needs_ to solve frontier challenges. ”Call to Jane”, ”turn on the lights” and ”what’s the weather this afternoon” is more like it I would guess.

      Ofc if the model has some critical bugs that’s another matter.

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    • And the customers can wait for the new phone released next year. These are edge models - the average customer doesn’t need the latest frontier model. Just needs to be good enough for the features you promised.

    • That's a software engineering problem. They just need to figure out how to fine-tune for alignment and tool usage.

      That's the only thing the normie consumer cares for really.

  • It is my understanding that just baking the model itself into silicon only gives moderate gains because memory bandwidth remains a bottleneck.