Comment by kayson
8 hours ago
Yes. There is exactly that, and we call it an "extraction" tool. It takes a GDS (text representation of shapes in the physical layout), and gives you back a "netlist" (text representation of components and connections in a circuit schematic).
Circuit designers use these tools basically daily for two reasons - the first is Layout Versus Schematic. We want to make sure that the physical layout matches the schematic, so the tool turns the layout GDS into a netlist and compares that to the netlist created from the schematic (basically a diff, but more complicated). The second is so we can run simulations that take into account the "parasitic" resistances and capacitances of the wires and metal shapes in the physical layout. It's basically the same procedure as LVS with an extra step that analyzes the metal shapes to determine said R's and C's.
yes, but at the transistor level .... it has no idea at that level how those transistors are arranged into gates directly
The tools can definitely recognize static logic gates purely from the topology (nothing special in the GDS needed). I don't know that I've tested it for anything more complicated, but as you've pointed out, if the hierarchy is in the GDS it's trivial to recover
I take it back, it's a sky130 .gds the gates are explicitly in there
In fact if you have the sky130 libraries installed (it's where I'm working) you can get a spice netlist out of it in about 10 seconds - really they should have flattened it