Comment by __d
2 days ago
So … use RISC-V as the strawman, and create a community-based RISC-6 that doesn’t have these weaknesses? Better to get in now before it becomes too solidly entrenched.
2 days ago
So … use RISC-V as the strawman, and create a community-based RISC-6 that doesn’t have these weaknesses? Better to get in now before it becomes too solidly entrenched.
Likely impossible unless you somehow come up with something vastly better (unlikely).
None of these things are remotely bad enough to make the downsides of using another ISA palatable.
How about EPIC-esque packet-based instructions?
64-bit instructions with 4 bits indicating instruction formats (60-bit, two 40+20-bit variants, 30+30-bit, 20+20+20-bit, three 30+15+15-bit variants, and 15+15+15+15-bit). Have each larger instruction type be a strict superset of the smaller instructions, but with larger immediates, more registers, and maybe additional instruction formats (eg, for SIMD).
Something like that would be even easier to decode (converting short instructions to long is simply a bit of wiring). Instruction density should increase due to 20-bit instruction type. Having properly-aligned instructions would help with fetching performance. Larger instructions means you can jump 4x further with the same immediate and 16-bit offsets. No need to have some of the V extension workarounds (from not wanting to add 48-bit instructions).
So a VLIW, interesting but usually compressed instructions are at most two-registers..
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Anther ISA like ARM? It seems pretty palatable to just about everyone not academic.
You're vastly underestimating the amount of work that has gone into RISC-V that would need to be redone. It's not just a spec. There's an absolute mountain of software and hardware supporting it.
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The ARM ISAs are not free to implement. ARM holds patents relevant to the ISA.
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And yet, new ISAs arise fairly regularly, for various reasons. RISC-V itself succeeded largely because it is gratis, I think.
You can't make a community-based ISA, it's not possible unless you have a community-based fab. He who makes the chips makes the rules.
Err … RISC-V is an ISA without a fab?
I mean, a shuttle run is pretty cheap these days. If you have silicon, and customers, scaling past a shuttle run that worked is pretty low additional cost.
It's not really a community though is it?