Comment by wren6991
2 days ago
You might find this relevant: RISC-V Genealogy (2016) https://riscv.org/wp-content/uploads/2025/02/EECS-2016-6.pdf
Or in poster form: https://riscv.org/wp-content/uploads/2025/02/RISC-V-Instruct...
2 days ago
You might find this relevant: RISC-V Genealogy (2016) https://riscv.org/wp-content/uploads/2025/02/EECS-2016-6.pdf
Or in poster form: https://riscv.org/wp-content/uploads/2025/02/RISC-V-Instruct...
Yeah, very much legally distinct MIPS, at least as a starting point.
The biggest tell is the mnemonics. While RISC-V takes a bunch of ideas from other places, and cleans things up, it copies a lot of mnemonics straight from MIPS.
But it also copies a lot of other ideas from MIPS, like the absolute distain for flag registers.
>absolute distain for flag registers
It's worst aspect maybe.
The RISC-V specs insist that this is important for simplifying high performance designs, because a flag register is a single piece of shared state that instructions are constantly (and often inadvertently!) touching. This necessarily introduces hazards and serialization.
I don’t know enough about high performance microarchitecture design to evaluate that argument confidently, but it seems to make sense to me.
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