Comment by p_l

X86 does not really need pipelined decoders like NVAX did. The complex decode for x86 is the fast path for NVAX without going into CSU. And CSU is where all the more complex addressing modes on VAX end up going - the complex instructions are executed, yes slowly, but in separate unit once CSU finishes the decode for them (and even for packed decimal stuff I-box can theoretically decode in nearly one cycle if all operands are register or immediate). uop cache I'd admit could help for some cases, but still leaves you with even a simple ADD instruction possibly expanding into ~7 uops, maybe 3-4 if we assume big fused equivalent of LEA but then 2 of those will still stall with memory requests.

DEC didn't try to parallelize the decoder further because it already could face 56 bytes for a single instruction, and the NVAX design was costly as hell. x86 in comparison has limit of max 15 bytes per instruction, and most instructions in x86 code fall in 4 bytes