Comment by PorciiVorbesc

Your theory that "1 shared FPU per module should equal 1 shared FPU per SMT core" makes sense on paper, but Bulldozer lost to Intel’s Sandy Bridge 4C/8T in floating-point and memory-heavy workloads because Intel's individual FPU, cache hierarchy, and front-end pipelines were vastly wider and faster than Bulldozer's shared components.

Having the same count of units (4 FPUs on the chip) did not mean having the same throughput. It's a HW bottleneck, not something AMD could fix via the OS's kernel allocation and scheduling of resources to the CPU to be able match Intel.

In strictly integer 4-8 thread benchmarks, yeah, AMD was often tied to Intel's 4C+SMT.

Bulldozer’s design didn't lose because the concept of sharing an FPU between two threads is worse than SMT. It lost because:

  Intel's FPU was natively twice as wide (256-bit vs. split 128-bit).

  AMD's write-through L1 cache caused catastrophic write contention in L2.

  AMD's L2 and L3 caches had double to triple the access latency of Intel's.

  A single shared 4-wide decoder couldn't feed an FPU and two integer units simultaneously.