Comment by the_why_of_y

Itanium failed to deliver on its basic promise: the simple in-order VLIW design was intended to be much easier to implement in hardware than the complex out-of-order RISC designs with long pipelines that everybody else (including Intel x86/AMD64) was doing, but then the various actual Itanium CPUs were notorious for being released years later than initially announced, and due to the delays the available out-of-order RISCs were usually much faster.