Comment by FullyFunctional
7 years ago
RISC-V is very VERY close to Alpha in this respect. There are no flags, everything is communicated via registers (which makes semantics clean and dynamic scheduling cheaper), and the equivalent of PALcode exist (called platform specific SBI calls, executing in M-mode).
IMhO, RISC-V is slightly better than Alpha on a many fronts: the conditional branches which compares two registers would take two instructions on Alpha (on the critical path), RISC-V code density is better with compressed, the encoding is slightly cheaper for hardware, it ISA is more forward-looking/extensible, oh and it's open of course. The only thing I miss are the POPC/CTZ/CLZ instructions, but the B set will include them for implementations that have it.
UPDATE: more RISC-V upsides
Also, RISC-V hasn't been bought, litigated, and buried. Alpha is great, but we're about as likely to get new implementations of it at this point as we are of the 6809 or v20.
RISC-V's future is looking better and better. Who knows? Maybe TSMC or Samsung or one of the smaller fabs puts out a multicore version on a fairly modern process node and gets a multi-player motherboard market built in Taipei, Seoul, and Shenzen. It could be a player in laptops, desktops, tablets, and mobile rather than just embedded and SBCs. It could even be done without a premium going to Intel, AMD, ARM, nVidia, TI, Freescale, or IBM. The possibilities are exciting, because every time I hear about this ISA and its implementations it's better news.