18 MHz, actually -- the FPGA clock speed is 73 MHz, but it executes the equivalent of one 6502 clock cycle in four of its clocks.
That being said, this was implemented on a budget-line FPGA from 2006 (XC3S50A - a small Xilinx Spartan-3A). A modern performance-line FPGA would probably hit a couple hundred MHz easily.
A new stock 65c02 from WDC can do 20mhz. So this FPGA version @ 18mhz doesn't sound any better. Though I'm sure on a modern FPGA one can do more than that.
18 MHz, actually -- the FPGA clock speed is 73 MHz, but it executes the equivalent of one 6502 clock cycle in four of its clocks.
That being said, this was implemented on a budget-line FPGA from 2006 (XC3S50A - a small Xilinx Spartan-3A). A modern performance-line FPGA would probably hit a couple hundred MHz easily.
It's still surprising how little relatively to the level of perceived performance have IPC count improved since seventies.
It seems to me that computational throughput has improved exponentially, but latency for input tasks etc. has in fact worsened in many cases.
Per TFA IPC has improved by about factor of 5, assuming a 3GHz machine runs BBC micro at equivalent performance of 15GHz
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You're wrong :)
IPCs for 6502 or Z80 (4x "faster" clock but 3-6 cycles per machine cycle) processors were at the count of clock cycles per instruction
Even a measly 386/486 were much faster than that.
Enter the Pentium with the ability to execute 2 instructions in parallel.
IPC count were the big gainers recently as well
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The perceived performance for an average desktop has been pretty stagnant since, I don't know, at least the mid-nineties.
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A new stock 65c02 from WDC can do 20mhz. So this FPGA version @ 18mhz doesn't sound any better. Though I'm sure on a modern FPGA one can do more than that.