Comment by leoc

Not an expert, but it seems that the size of the logic wafer is locked to the size of the pixel wafer in Sony's CMOS image sensors? https://fuse.wikichip.org/news/763/iedm-2017-sonys-3-layer-s... ? It seems that 65nm was current-generation for CISes in 2018: https://www.azom.com/article.aspx?ArticleID=16321 .