Comment by Tempest1981
2 years ago
I'm curious about the 9-layer PCBA -- is it an amplifier or signal conditioner, to achieve 40 Gb/s? Or does it implement some protocol?
Or for power delivery? I see what might be resistors or capacitors. Not sure what else.
It’s most likely 9-layers because that what you need to correctly route the traces from one set of 12 pins, to the other set of 12 pins (to make up the 24 total in USB-C), which is needed to make the connector fully reversible. There will also be a e-mark chip in there that tells any connected device what the cable is capable of doing, so you don’t accidentally send 240w down a cable only capable of carrying 100w.
9 layers might sounds like a lot. But reversible connectors are a bit of a logistical nightmare from a PCB routing perspective. Made even more complicated by the very tight signalling requirements needed to hit Thunderbolt 4 transfer speeds. The end result is what looks like a significant over-engineering, but is really just an expression of how difficult it is to transport high data rate signals around PCBs and cables.
Only 2 data pins per side are reversible that way, and it's the low speed ones.
The high speed pins (4 per side) should be going directly into a multiplexer or driver, the CC pins (1 per side) detect orientation, the sideband pins (1 per side) are only used dual-sided, and the power and ground pins (4 per side) aren't fussy at all.
That's not how USB-C works.
Unlike Apple's late Lightning connector, USB-C isn't two sets of mirrored pins. The power pins are simply shorted together on both sides, four pins each for VBUS and GND. USB2 and CC (connection detection) are connected only on one side. The remaining pins are four high-speed lanes, two per side.
With rare exceptions, a USB-C cable does not do anything about reversibility. It simply connects the pins straight-trough to its partner on the other plug. The lane swapping needed for the high-speed lanes is done by the devices, not the cable.
The Apple cable is so complicated because it is a 40Gbps cable over 100cm long. This means it requires a redriver to guarantee signal integrity. That's what the big chip is for. Doing that in the small space available in a plug means your routing gets complicated.
> The end result is what looks like a significant over-engineering, but is really just an expression of how difficult it is to transport high data rate signals around PCBs and cables.
It's not just that. If it was just data speeds that's way easier, passive 10/40GBit DAC cables have been there for long time, they just use twinax (2 wire coax cable instead of differential pairs IIRC) and can go up to 7m passive, but that makes for not so bendy cable.
But USB-C so much more than few data lines, high power, legacy USB2, power negotiation and various alternate functions all in same connection.
The sibling reply is certainly correct - all those high speed signals need room, plus adjacent reference planes for good signal integrity. The power distribution also probably needs a lot of copper for the relatively high current the board sees.
That being said, an odd number of metal layers is very unlikely. It's physically possible but due to the lamination process, PCBs are basically always built in an even number of layers. It's a bit tough to tell with the resolution of the scan, but it looks like the dielectric layers were counted as 9, giving 10 total metal layers.