Comment by BearOso
2 years ago
I don't understand how the author goes from 3.8 WAF(Write Amplication Factor) to 2.0 WAF and gets a 30x increase in endurance. I'd expect about 2x from that.
From what I can see, he seems to be taking the 120TBW that the OEM warranties on the drive for the initial result, but then using the NAND's P/E cycles spec for the final result, which seems suspicious.
The only thing that I could be missing is the NAND going to pSLC mode somehow increases the P/E cycles drastically, like requiring massively lower voltage to program the cells. But I think that would be included in the WAF measure.
What am I missing?
QLC memory cells need to store and read back the voltage much more precisely than SLC memory cells. You get far more P/E cycles out of SLC because answering "is this a zero or a one?" remains fairly easy long after the cells are too worn to reliably distinguish between sixteen different voltage levels.
the author is wrong. what you mention is only true for actual SLC chip+firmware. qlc drivers probably don't even have the hardware to use the entire cell as slc, and they adopt one of N methods to save time/writes/power by underutilizing the resolution of the cell. neither gives you all the benefits, all increases the downsides to improve one upside.
and you can't choose.
Even if they do it in a slapdash way, it's still going to be 0 versus "pretty high" and that's a lot easier than gradients of 16ths. Dropping the endurance to match QLC mode would require intentional effort.
what's missing here: QLC bit is not 4-nery, it's 4 bit per bit. 2^4 = 16, so it's actually 16LC. That's contradictory to the name "quad level cell", yes, for some reason.
Respectfully: to the extent that I can understand what you're trying to say, you don't seem to know what you're talking about. Stop trying so hard to bash the whole industry for making tradeoffs you don't agree with, and put a little more effort into understanding how these things actually work.
3 replies →