Comment by mastax

Karliss above found docs which mention:

> This request requires up to three timer clock cycles. If the selected timer is working at slow clock, the request could take longer.

Let's ignore the weirdly ambiguous second sentence and say for pedagogical purposes it takes up to three timer clock cycles full stop. Timer clock cycles aren't CPU clock cycles, so we can't just do `nop; nop; nop;`. How do we wait three timer clock cycles? Well a timer register read is handled by the timer peripheral which runs at the timer clock, so reading (or writing) a timer register will take until at least the end of the next timer clock.

This is a very common pattern when dealing with memory mapped peripheral registers.

---

I'm making some reasonable assumptions about how the clock peripheral works. I haven't actually dug into the Marvell documentation.